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Data Fields</h2></td></tr>
<tr class="memitem:a3fd1bb0f1355b276eb5ebad802dc0d3c"><td class="memItemLeft" align="right" valign="top">u64&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_vphy___channel.html#a3fd1bb0f1355b276eb5ebad802dc0d3c">LineRateHz</a></td></tr>
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<tr class="memitem:ade5f05b304aa05b950d87d47f80e4415"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_vphy___channel.html#ade5f05b304aa05b950d87d47f80e4415">RxOutDiv</a></td></tr>
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<tr class="memitem:ab9ec1df65ce5279c9ab36e6d68d2cf1d"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_vphy___channel.html#ab9ec1df65ce5279c9ab36e6d68d2cf1d">RxDelayBypass</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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          <td class="memname"><a class="el" href="struct_x_vphy___pll_param.html">XVphy_PllParam</a> XVphy_Channel::CpllParams</td>
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<p>Parameters for a CPLL. </p>

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          <td class="memname"><a class="el" href="xvphy_8h.html#abaf929d37e9f193c5577e3a08b50c950">XVphy_PllRefClkSelType</a> XVphy_Channel::CpllRefClkSel</td>
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<p>Multiplexer selection for the reference clock of the CPLL. </p>

<p>Referenced by <a class="el" href="xvphy__gthe2_8c.html#ab6312a563d776bff4bb8e832509ab3a1">XVphy_Gthe2CfgSetCdr()</a>, <a class="el" href="xvphy__gthe3_8c.html#a75a9c18216055207d1cf78fc0d5b6eee">XVphy_Gthe3CfgSetCdr()</a>, and <a class="el" href="xvphy_8h.html#a5041cead7e1fe927d645c4e681e95837">XVphy_WriteCfgRefClkSelReg()</a>.</p>

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<p>The line rate for the channel. </p>

<p>Referenced by <a class="el" href="xvphy_8h.html#ad5d2ef80f68b92db024b3e690d0c410e">XVphy_CfgLineRate()</a>, <a class="el" href="xvphy__hdmi_8c.html#a9bda272cbcfb83ee43e762b09e613390">XVphy_HdmiCfgCalcMmcmParam()</a>, and <a class="el" href="xvphy__hdmi_8c.html#afe03e6d04132bfe780efa1a2708ded64">XVphy_SetHdmiTxParam()</a>.</p>

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          <td class="memname"><a class="el" href="xvphy_8h.html#a91d7e180fc85dbee0c2daeb6014597c0">XVphy_SysClkDataSelType</a> XVphy_Channel::RxDataRefClkSel</td>
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<p>Multiplexer selection for the reference clock of the RX datapath. </p>

<p>Referenced by <a class="el" href="xvphy__dp_8c.html#a1467ac8d01eee6591cee4c820d55c093">XVphy_DpDebugInfo()</a>, <a class="el" href="xvphy__hdmi_8c.html#ac33c4acc75ec57ab3d51e0f1391f1baf">XVphy_HdmiDebugInfo()</a>, and <a class="el" href="xvphy_8h.html#a5041cead7e1fe927d645c4e681e95837">XVphy_WriteCfgRefClkSelReg()</a>.</p>

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          <td class="memname">u8 XVphy_Channel::RxDataWidth</td>
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<p>In bits. </p>

<p>Referenced by <a class="el" href="xvphy__gthe3_8c.html#ac3bf439d3845203fb9a60463df024eb3">XVphy_Gthe3RxChReconfig()</a>, <a class="el" href="xvphy__hdmi_8h.html#ab0c73c2bc8e97b64dd7509cd3db6b39c">XVphy_HdmiCpllParam()</a>, and <a class="el" href="xvphy__hdmi_8h.html#ae51de602190f2058b30e0801deb13fa9">XVphy_HdmiQpllParam()</a>.</p>

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<p>Bypasses the delay alignment block for the RX output clock. </p>

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<p>In bytes. </p>

<p>Referenced by <a class="el" href="xvphy__gthe3_8c.html#ac3bf439d3845203fb9a60463df024eb3">XVphy_Gthe3RxChReconfig()</a>, <a class="el" href="xvphy__hdmi_8h.html#ab0c73c2bc8e97b64dd7509cd3db6b39c">XVphy_HdmiCpllParam()</a>, and <a class="el" href="xvphy__hdmi_8h.html#ae51de602190f2058b30e0801deb13fa9">XVphy_HdmiQpllParam()</a>.</p>

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          <td class="memname"><a class="el" href="xvphy_8h.html#ae82c27883add3fd1d30d4e0a8d5ee869">XVphy_OutClkSelType</a> XVphy_Channel::RxOutClkSel</td>
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<p>Multiplexer selection for which clock to use as the RX output clock. </p>

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<p>Output clock divider D for the RX datapath. </p>

<p>Referenced by <a class="el" href="xvphy__dp_8c.html#a1467ac8d01eee6591cee4c820d55c093">XVphy_DpDebugInfo()</a>, <a class="el" href="xvphy__hdmi_8h.html#ad88e970b83779757b2cf739b3aaeb9a9">XVphy_DruCalcCenterFreqHz()</a>, <a class="el" href="xvphy__gthe3_8c.html#a75a9c18216055207d1cf78fc0d5b6eee">XVphy_Gthe3CfgSetCdr()</a>, <a class="el" href="xvphy__gtxe2_8c.html#ace4c94fe749921ba346ce93f7ff9ff16">XVphy_Gtxe2CfgSetCdr()</a>, and <a class="el" href="xvphy__hdmi_8c.html#ac33c4acc75ec57ab3d51e0f1391f1baf">XVphy_HdmiDebugInfo()</a>.</p>

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          <td class="memname"><a class="el" href="xvphy_8h.html#a1ff2690f40dd23e3fb4ba55d99a6c45f">XVphy_SysClkOutSelType</a> XVphy_Channel::RxOutRefClkSel</td>
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<p>Multiplexer selection for the reference clock of the RX output clock. </p>

<p>Referenced by <a class="el" href="xvphy_8h.html#a5041cead7e1fe927d645c4e681e95837">XVphy_WriteCfgRefClkSelReg()</a>.</p>

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          <td class="memname"><a class="el" href="xvphy_8h.html#a1018e4be67be76fe085dc41338285bd2">XVphy_ProtocolType</a> XVphy_Channel::RxProtocol</td>
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<p>The protocol which the RX path is used for. </p>

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          <td class="memname"><a class="el" href="xvphy_8h.html#a11be9fb60860466de1747a062ac1a919">XVphy_GtState</a> XVphy_Channel::RxState</td>
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<p>Current state of RX GT. </p>

<p>Referenced by <a class="el" href="xvphy__dp_8c.html#a2cd0f5a7bf8d8fb14c73dff670c3c998">XVphy_DpInitialize()</a>, <a class="el" href="xvphy__hdmi__intr_8c.html#af3406907d051c798f74f8bb569c4261c">XVphy_HdmiCpllLockHandler()</a>, <a class="el" href="xvphy__hdmi__intr_8c.html#a2e9bd9101245bba02f36126695b9cf61">XVphy_HdmiGtRxResetDoneLockHandler()</a>, <a class="el" href="xvphy__hdmi_8c.html#acd09bca6664c614b29cf051367729ea3">XVphy_HdmiInitialize()</a>, <a class="el" href="xvphy__hdmi__intr_8c.html#a8bd66d9c2cc594b160462de216f92aac">XVphy_HdmiQpllLockHandler()</a>, <a class="el" href="xvphy__hdmi__intr_8c.html#a13246516a638f38a679c7fedb702ef64">XVphy_HdmiRxClkDetFreqChangeHandler()</a>, <a class="el" href="xvphy__hdmi__intr_8c.html#ac6db7053df3c70a865717c47ba18eea3">XVphy_HdmiRxTimerTimeoutHandler()</a>, and <a class="el" href="xvphy__hdmi_8c.html#ab70418575e7ffd80d353f12e666dd483">XVphy_HdmiUpdateClockSelection()</a>.</p>

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          <td class="memname"><a class="el" href="xvphy_8h.html#a91d7e180fc85dbee0c2daeb6014597c0">XVphy_SysClkDataSelType</a> XVphy_Channel::TxDataRefClkSel</td>
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<p>Multiplexer selection for the reference clock of the TX datapath. </p>

<p>Referenced by <a class="el" href="xvphy__dp_8c.html#a1467ac8d01eee6591cee4c820d55c093">XVphy_DpDebugInfo()</a>, <a class="el" href="xvphy__hdmi_8c.html#ac33c4acc75ec57ab3d51e0f1391f1baf">XVphy_HdmiDebugInfo()</a>, and <a class="el" href="xvphy_8h.html#a5041cead7e1fe927d645c4e681e95837">XVphy_WriteCfgRefClkSelReg()</a>.</p>

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<p>Bypasses the delay alignment block for the TX output clock. </p>

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          <td class="memname"><a class="el" href="xvphy_8h.html#ae82c27883add3fd1d30d4e0a8d5ee869">XVphy_OutClkSelType</a> XVphy_Channel::TxOutClkSel</td>
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<p>Multiplexer selection for which clock to use as the TX output clock. </p>

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<p>Output clock divider D for the TX datapath. </p>

<p>Referenced by <a class="el" href="xvphy__dp_8c.html#a1467ac8d01eee6591cee4c820d55c093">XVphy_DpDebugInfo()</a>, <a class="el" href="xvphy__hdmi_8c.html#ac33c4acc75ec57ab3d51e0f1391f1baf">XVphy_HdmiDebugInfo()</a>, and <a class="el" href="xvphy__hdmi__intr_8c.html#aa0d8603249cf47b026958d23acc5ed7e">XVphy_HdmiTxTimerTimeoutHandler()</a>.</p>

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          <td class="memname"><a class="el" href="xvphy_8h.html#a1ff2690f40dd23e3fb4ba55d99a6c45f">XVphy_SysClkOutSelType</a> XVphy_Channel::TxOutRefClkSel</td>
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<p>Multiplexer selection for the reference clock of the TX output clock. </p>

<p>Referenced by <a class="el" href="xvphy_8h.html#a5041cead7e1fe927d645c4e681e95837">XVphy_WriteCfgRefClkSelReg()</a>.</p>

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          <td class="memname"><a class="el" href="xvphy_8h.html#a1018e4be67be76fe085dc41338285bd2">XVphy_ProtocolType</a> XVphy_Channel::TxProtocol</td>
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<p>The protocol which the TX path is used for. </p>

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          <td class="memname"><a class="el" href="xvphy_8h.html#a11be9fb60860466de1747a062ac1a919">XVphy_GtState</a> XVphy_Channel::TxState</td>
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<p>Current state of TX GT. </p>

<p>Referenced by <a class="el" href="xvphy__dp_8c.html#a2cd0f5a7bf8d8fb14c73dff670c3c998">XVphy_DpInitialize()</a>, <a class="el" href="xvphy__hdmi__intr_8c.html#af3406907d051c798f74f8bb569c4261c">XVphy_HdmiCpllLockHandler()</a>, <a class="el" href="xvphy__hdmi__intr_8c.html#a2e9bd9101245bba02f36126695b9cf61">XVphy_HdmiGtRxResetDoneLockHandler()</a>, <a class="el" href="xvphy__hdmi__intr_8c.html#ae97beeed4294d08e6afb698c35dd5810">XVphy_HdmiGtTxAlignDoneLockHandler()</a>, <a class="el" href="xvphy__hdmi__intr_8c.html#ab72b8270889de157c711c3502ad38104">XVphy_HdmiGtTxResetDoneLockHandler()</a>, <a class="el" href="xvphy__hdmi_8c.html#acd09bca6664c614b29cf051367729ea3">XVphy_HdmiInitialize()</a>, <a class="el" href="xvphy__hdmi__intr_8c.html#a8bd66d9c2cc594b160462de216f92aac">XVphy_HdmiQpllLockHandler()</a>, <a class="el" href="xvphy__hdmi__intr_8c.html#ac4c46549ed36e875129093896382a039">XVphy_HdmiTxClkDetFreqChangeHandler()</a>, <a class="el" href="xvphy__hdmi__intr_8c.html#aa0d8603249cf47b026958d23acc5ed7e">XVphy_HdmiTxTimerTimeoutHandler()</a>, and <a class="el" href="xvphy__hdmi_8c.html#ab70418575e7ffd80d353f12e666dd483">XVphy_HdmiUpdateClockSelection()</a>.</p>

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